CP-PACS computer


Theoretical peak speed
614.4GFLOPS(*) (64bit data , 2048PU)
Total main memory
Node processor Architecture
Custom designed MPU based on PA-RISC 1.1
with PVP-SW feature
Floating point registers 128(64bit) physical registers
Clock cycle 150MHz
Cache memory size
First-level Instructions 16KByte
Data 16KByte
Second-level Instructions 512KByte
Data 512KByte
Network Topology
3-dimensional Hyper Crossbar (8x17x16)
Data transfer throughput 300MByte/sec (per link)
Method wormhole +remote DMA
Disk system 529GByte(distributed RAID-5 disk)
External connection HIPPI Theoretical peak throughput 100Mbyte/sec
Ethernet Theoretical peak throughput 1.2Mbyte/sec
Size 7.0m(width)x4.2m(depth)x2.0m(height)
Power dissipation 275 kW maximum

(*)GFLOPS : unit of one billion floating point operations per second. 600GFLOPS equals 600 billion operations each second.

Further details

Development of Parallel Computer and CP-PACS

October 1996

Back to the CCP home page